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NCP5214 Product Preview 2-in-1 Notebook DDR Power Controller
The NCP5214 2-in-1 Notebook DDR Power Controller is specifically designed as a total power solution for notebook DDR memory system. This IC combines the efficiency of a PWM controller for the VDDQ supply with the simplicity of linear regulators for the VTT termination voltage and the buffered low noise reference. This IC contains a synchronous PWM buck controller for driving two external NFETs to form the DDR memory supply voltage (VDDQ). The DDR memory termination regulator output voltage (VTT) and the buffered VREF are internally set to track at the half of VDDQ. An internal power good voltage monitor tracks VDDQ output and notifies the user whether the VDDQ output is within target range. Protective features include soft-start circuitries, undervoltage monitoring of supply voltage, VDDQ overcurrent protection, VDDQ overvoltage and undervoltage protections, and thermal shutdown. The IC is packaged in DFN-22.
Features http://onsemi.com MARKING DIAGRAM
22 DFN-22 MN SUFFIX CASE 506AF 1 NCP5214 AWLYYWW
1
NCP5214 A WL YY WW
= Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week
* * * * * * * * * * * * * * * * *
Incorporates VDDQ, VTT Regulator, Buffered VREF Adjustable VDDQ Output VTT and VREF Track VDDQ/2 Operates from Single 5.0 V Supply Supports VDDQ Conversion Rails from 5.0 V to 24 V Power-saving Mode for High Efficiency at Light Load Integrated Power FETs with VTT Regulator Sourcing/Sinking 1.5 A DC and 2.4 A Peak Current Buffered Low Noise 15 mA VREF Output All External Power MOSFETs are N-channel <5.0 mA Current Consumption During Shutdown Fixed Switching Frequency of 400 kHz Soft-start Protection for VDDQ and VTT Undervoltage Monitor of Supply Voltage Overvoltage Protection and Undervoltage Protection for VDDQ Short-circuit Protection for VDDQ and VTT Thermal Shutdown Housed in DFN-22
PIN CONNECTIONS
VDDQEN VTTEN FPWM SS VTTGND VTT VTTI FBVTT AGND DDQREF VCCA (Top View) NOTE: Pin 23 is the thermal pad on the bottom of the device. PGND BGDDQ VCCP SWDDQ TGDDQ BOOST OCDDQ PGOOD VTTREF FBDDQ COMP
ORDERING INFORMATION
Device NCP5214MNR2 Package DFN-22 Shipping 2500 Tape & Reel
Typical Applications
* Notebook DDR/DDR2 Memory Supply and Termination Voltage * Active Termination Busses (SSTL-18, SSTL-2, SSTL-3)
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D.
This document contains information on a product under development. ON Semiconductor reserves the right to change or discontinue this product without notice.
(c) Semiconductor Components Industries, LLC, 2005
1
April, 2005 - Rev. P0
Publication Order Number: NCP5214/D
NCP5214
CL1 VDDQEN VTTEN FPWM VDDQEN VTTEN FPWM SS BOOST CSS OCDDQ 5VCC RL1
5VCC
VCCP
VIN 5 V to 24 V (Battery/ Adapter) L 1.8 mH M2 COUT1 POSCAP 150 mF x2 VDDQ 1.8 V, 10 A
PWRGD PGOOD 0.9 V, 2.4 Apk COUT2 Ceramic 22 mF x2 5VCC VCCA COMP CZ1 CP1 RZ1 VTTREF FBDDQ VTT VTT TGDDQ SWDDQ BGDDQ PGND1
M1
NCP5214
FBVTT VTTGND
CZ2 RZ2
R1
VREF 0.9 V, 15 mA
R2
DDQREF
AGND
VTTI
Figure 1. Typical Application Diagram
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NCP5214
5VCC VREF VDDQEN VIN
VOLTAGE & CURRENT REFERENCE
VREFGD VDDQEN TSD VTTEN FPWM VCCAGD VOCDDQGD FAULT
THERMAL SHUTDOWN
CBULK VCCP VCCP VBOOST BOOST 5VCC
VTTEN FPWM VCCA VCCA
CONTROL LOGIC
VREF
ILIM
VOFFSET
+ -
RL1 IREF VBOOST OCDDQ
VOCDDQ
VREF
+ -
VCCA VDDQEN VTTEN
VDDQ PWM LOGIC
M3 FBDDQ SWDDQ TGDDQ L SWDDQ VCCP NEGATIVE CURRENT DETECTION M4 BGDDQ PGND PGND VREF VFBDDQ COUT1 VDDQ
SS
Power- Saving Loop Control
+ -
5VCC
PGOOD
PWM- COMP
+-
UVLO
+ -
OVLO
VFBDDQ
+ -
VREF
OSC
PGND VOCDDQ VREF COMP CZ1 RZ1 FBDDQ R2 CZ2 CP1 RZ2 R1
Adaptive Ramp
A
+ -
+ -
VTTI
Current Limit & Soft-Start
SC2PWR VDDQEN VTTEN INREGDDQ
DDQREF VCCA M1 VTTI VTT
VTTREF VTTREF COUT3
+ -
Deadband Control
VTT Regulation Control
VTTGND VTT VCCA M2 COUT2
+ -
SC2GND VTTGND VTTGND FBVTT VTTGND
PGND
GND
AGND
VTTGND
Figure 2. Detailed Block Diagram
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CDCPL
CBOOST
+ -
INREGDDQ
+ -
NCP5214
PIN FUNCTION DESCRIPTION
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Symbol VDDQEN VTTEN FPWM SS VTTGND VTT VTTI FBVTT AGND DDQREF VCCA COMP FBDDQ VTTREF PGOOD OCDDQ Description VDDQ regulator enable input. High to enable. VTT regulator enable input. High to enable. Forced PWM enable input. Low to enable forced PWM mode and disable power-saving mode. VDDQ Soft-start capacitor connection to ground. Power ground for the VTT regulator. VTT regulator output. Power input for VTT regulator which is normally connected to the VDDQ output of the buck regulator. VTT regulator feedback pin for closed loop regulation. Analog ground connection and remote ground sense. External reference input which is used to regulate VTT and VTTREF to 1/2VDDQREF. 5.0 V supply input for the IC's control and logic section, which is monitored by undervoltage lock out circuitry. VDDQ error amplifier compensation node. VDDQ regulator feedback pin for closed loop regulation. DDR reference voltage output. Power good signal open-drain output. Overcurrent sense and program input for the high-side FET of VDDQ regulator. Also the battery voltage input for the internal ramp generator to implement the voltage feedforward rejection to the input voltage variation. Positive supply input for high-side gate driver of VDDQ regulator and boost capacitor connection. Gate driver output for VDDQ regulator high-side N-Channel power FET. VDDQ regulator inductor driven node, return for high-side gate driver, and current limit sense input. Power supply for the VDDQ regulator low-side gate driver and also supply voltage for the bootstrap capacitor of the VDDQ regulator high-side gate driver supply. Gate driver output for VDDQ regulator low-side N-Channel power FET. Power ground for the VDDQ regulator. Copper pad on bottom of IC used for heatsinking. This pin should be connected to the ground plane under the IC.
17 18 19 20 21 22 23
BOOST TGDDQ SWDDQ VCCP BGDDQ PGND THPAD
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NCP5214
MAXIMUM RATINGS
Rating Power Supply Voltage (Pin 11, 20) to AGND (Pin 9) High-Side Gate Drive Supply: BOOST (Pin 17) to SWDDQ (Pin 19) High-Side FET Gate Drive Voltage: TGDDQ (Pin 18) to SWDDQ (Pin 19) Input/Output Pins to AGND (Pin 9) Pins 1-4, 6-8, 10, 12-15, 21 Overcurrent Sense Input (Pin 16) to AGND (Pin 9) Switch Node (Pin 19) PGND (Pin 22), VTTGND (Pin 5) to AGND (Pin 9) Thermal Characteristics DFN-22 Plastic Package Thermal Resistance, Junction-to-Ambient Operating Junction Temperature Range Operating Ambient Temperature Range Storage Temperature Range Moisture Sensitivity Level Symbol VCCA, VCCP VBOOST-VSWDDQ, VTGDDQ-VSWDDQ VIO VOCDDQ VSWDDQ VGND RqJA Value -0.3, 6.0 -0.3, 6.0 -0.3, 6.0 27 -4.0 (<100 ns), 0.3 (dc), 32 -0.3, 0.3 35 Unit V V V V V V _C/W
TJ TA Tstg MSL
0 to +150 -40 to +85 -55 to +150 2
_C _C _C -
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. 1. This device series contains ESD protection and exceeds the following tests: Human Body Model (HBM) 2.0 kV per JEDEC standard: JESD22-A114. Machine Model (MM) 200 V per JEDEC standard: JESD22-A115. 2. Latchup Current Maximum Rating: 150 mA per JEDEC standard: JESD78.
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NCP5214
ELECTRICAL CHARACTERISTICS (VIN = 12 V, TA = -40 to 85_C, VCCA = VCCP = VBOOST - VSWDDQ = 5.0 V, L = 1.8 mH, COUT1 = 150 mF x 2, COUT2 = 22 mF x 2, RL1 = 1.0 kW, R1 = 4.3 kW, R2 = 3.3 kW, RZ1 = 6.2 kW, RZ2 = 130 W, CP1 = 100 pF, CZ1 = 2.2 nF, CZ2 = 4.7 nF, for min/max values unless otherwise noted. Typical values are at TA = 25_C.)
Characteristic SUPPLY VOLTAGE Input Voltage VCCA Operating Voltage VCCP Operating Voltage SUPPLY CURRENT VCCA Quiescent Supply Current in S0 VCCA Quiescent Supply Current in S3 VCCA Shutdown Current VCCP Quiescent Supply Current in S0 VCCP Quiescent Supply Current in S3 VCCP Shutdown Current UNDERVOLTAGE MONITOR VCCA UVLO Lower Threshold VCCA UVLO Hysteresis VOCDDQ UVLO Upper Threshold VOCDDQ UVLO Hysteresis THERMAL SHUTDOWN Thermal Trip Point Hysteresis VDDQ SWITCHING REGULATOR FBDDQ Feedback Voltage, Control Loop in Regulation Feedback Input Current Oscillator Frequency Ramp Amplitude Voltage Ramp Amplitude to VIN Ratio OCDDQ Pin Current Sink OCDDQ Pin Current Sink Temperature Coefficient Minimum On Time Maximum Duty Cycle VFBDDQ Ifb FSW Vramp dVRAMP/dVIN IOC TCIOC tonmin Dmax TA = 25C TA = -40 to 85C VFBDDQ = 0.8 V - VIN = 5.0 V (Note 3) - VOCDDQ = 4.0 V TA = -40 to 85C - VIN = 5.0 V VIN = 15 V VIN = 24 V VDDQEN = 5.0 V, Vss = 0 V With Respect to Error Comparator Threshold of 0.8 V With Respect to Error Comparator Threshold of 0.8 V 0.788 0.780 - 340 - - 23 - - - - - 3.5 115 - 0.8 0.8 - 400 1.25 45 35 3200 150 90 50 32 5.0 130 65 0.812 0.820 1.0 460 - - 47 - - - - - 6.5 - 75 V mA kHz V mV/V mA ppm/ _C ns % TSD TSDHYS (Note 3) (Note 3) - - 150 25 - - _C _C VCCAUV- VCCAUVHYS VOCDDQUV+ VOCDDQUVHYS Falling Edge - Rising Edge - - - - - 3.7 0.35 3.5 0.2 4.1 - - - V V V V IVCCA_S0 IVCCA_S3 IVCCA_SD IVCCP_S0 IVCCP_S3 IVCCP_SD VDDQEN = 5.0 V, VTTEN = 5.0 V VDDQEN = 5.0 V, VTTEN = 0 V VDDQEN = 0 V, VTTEN = 0 V VDDQEN = 5.0 V, VTTEN = 5.0 V, TGDDQ and BGDDQ Open VDDQEN = 5.0 V, VTTEN = 0 V, TGDDQ and BGDDQ Open VDDQEN = 0 V, VTTEN = 0 V - - - - - - 5.0 - - - - - 10 5.0 4.0 20 20 1.0 mA mA mA mA mA mA VIN VCCA VCCP - - - 4.5 4.5 4.5 - 5.0 5.0 24 5.5 5.5 V V V Symbol Test Conditions Min Typ Max Unit
Soft-Start Current Overvoltage Trip Threshold Undervoltage Trip Threshold 3. Guaranteed by design, not tested in production.
Iss FBOVPth FBUVPth
mA % %
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NCP5214
ELECTRICAL CHARACTERISTICS (continued) (VIN = 12 V, TA = -40 to 85_C, VCCA = VCCP = VBOOST - VSWDDQ = 5.0 V, L = 1.8 mH, COUT1 = 150 mF x 2, COUT2 = 22 mF x 2, RL1 = 1.0 kW, R1 = 4.3 kW, R2 = 3.3 kW, RZ1 = 6.2 kW, RZ2 = 130 W, CP1 = 100 pF, CZ1 = 2.2 nF, CZ2 = 4.7 nF, for min/max values unless otherwise noted. Typical values are at TA = 25_C.)
Characteristic ERROR AMPLIFIER DC Gain Unity Gain Bandwidth Slew Rate GATE DRIVERS TGDDQ Gate Pull-HIGH Resistance RH_TG VBOOST - VSWDDQ = 5.0 V, VTGDDQ - VSWDDQ = 4.0 V VBOOST - VSWDDQ = 5.0 V, VTGDDQ - VSWDDQ = 1.0 V VCCP = 5.0 V, VBGDDQ = 4.0 V VCCP = 5.0 V, VBGDDQ = 1.0 V - 1.8 - W GAIN Ft SR (Note 4) COMP_GND = 220 nF, 1.0 W in Series (Note 4) (Note 4) - - - 70 2.0 3.0 - - - dB MHz V/mS Symbol Test Conditions Min Typ Max Unit
TGDDQ Gate Pull-LOW Resistance BGDDQ Gate Pull-HIGH Resistance BGDDQ Gate Pull-LOW Resistance VTT ACTIVE TERMINATOR VTT with Respect to 1/2VDDQREF
RL_TG RH_BG RL_BG
- - -
1.8 1.8 0.9
- - -
W W W
dVTT0
1/2VDDQREF - VTT, VDDQREF = 2.5 V, IVTT = 0 to 2.4 A (Sink Current) IVTT = 0 to -2.4 A (Source Current) 1/2VDDQREF - VTT, VDDQREF = 1.8 V, IVTT = 0 to 2.0 A (Sink Current) IVTT = 0 to -2.0 A (Source Current)
mV
-30 -
- -
- 30 mV
-30 - - 2.5 2.5 - -
- - 50 3.0 3.0 1.0 1.0
- 30 - - - - - kW A A A ms
DDQREF Input Resistance Source Current Limit Sink Current Limit Soft-Start Source Current Limit Maximum Soft-Start Time VTTREF OUTPUT VTTREF Source Current VTTREF Accuracy Referred to 1/2VDDQREF
DDQREF_R ILIMVTsrc ILIMVTsnk ILIMVTSS tssvttmax
- - - - -
IVTTR dVTTR
VDDQREF = 1.8 V or 2.5 V 1/2VDDQREF - VTTR, VDDQREF = 2.5 V, IVTTR = 0 mA to 15 mA 1/2VDDQREF - VTTR, VDDQREF = 1.8 V, IVTTR = 0 mA to 15 mA
15 -25
- -
- 25
mA mV
-18
-
18
mV
4. Guaranteed by design, not tested in production.
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NCP5214
ELECTRICAL CHARACTERISTICS (continued) (VIN = 12 V, TA = -40 to 85_C, VCCA = VCCP = VBOOST - VSWDDQ = 5.0 V, L = 1.8 mH, COUT1 = 150 mF x 2, COUT2 = 22 mF x 2, RL1 = 1.0 kW, R1 = 4.3 kW, R2 = 3.3 kW, RZ1 = 6.2 kW, RZ2 = 130 W, CP1 = 100 pF, CZ1 = 2.2 nF, CZ2 = 4.7 nF, for min/max values unless otherwise noted. Typical values are at TA = 25_C.)
Characteristic CONTROL SECTION VDDQEN Pin Threshold High VDDQEN Pin Threshold Low VDDQEN Pin Input Current VTTEN Pin Threshold High VTTEN Pin Threshold Low VTTEN Pin Input Current PGOOD Pin ON Resistance PGOOD Pin OFF Current PGOOD LOW-to-HIGH Hold Time, for S5 to S0 5. Guaranteed by design, not tested in production. VDDQEN_H VDDQEN_L IIN_ VDDQEN VTTEN_H VTTEN_L IIN_VTTEN PGOOD_R PGOOD_LK thold - - VDDQEN = 5.0 V - - VDDQEN = VTTEN = 5.0 V I_PGOOD = 5.0 mA - (Note 5) 1.4 - - 1.4 - - - - - - - - - - - 80 - - - 0.5 0.5 - 0.5 0.5 - 1.0 200 V V mA V V mA W mA ms Symbol Test Conditions Min Typ Max Unit
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NCP5214
DETAILED OPERATING DESCRIPTION
General
The NCP5214 2-in-1 Notebook DDR Power Controller combines the efficiency of a PWM controller for the VDDQ supply, with the simplicity of using a linear regulator for the VTT termination voltage power supply. The VDDQ output can be adjusted through the external potential divider, while the VTT is internally set to track half VDDQ. The inclusion of VDDQ power good voltage monitor, soft-start, VDDQ overcurrent protection, VDDQ overvoltage and undervoltage protections, supply undervoltage monitor, and thermal shutdown makes this device a total power solution for high current DDR memory system. The IC is packaged in DFN-22.
Control Logic
The internal control logic is powered by VCCA. The IC is enabled whenever VDDQEN is high (exceed 1.4 V). An internal bandgap voltage, VREF, is then generated. Once VREF reaches its regulation voltage, an internal signal VREFGD will be asserted. This transition wakes up the supply undervoltage monitor blocks, which will assert VCCAGD if VCCA voltage is within certain preset levels. The control logic accepts external signals at VCCA, OCDDQ, VDDQEN, VTTEN, and FPWM pins to control the operating state of the VDDQ and VTT regulators in accordance with Table 1. A timing diagram is shown in Figure 3.
VDDQ Switching Regulator in Normal Mode (S0)
VDDQ output voltage is divided down and fed back to the inverting input of an internal error amplifier through FBDDQ pin to close the loop at VDDQ = VFBDDQ x (1 + R2/R1). This amplifier compares the feedback voltage with an internal VREF (= 0.800 V) to generate an error signal for the PWM comparator. This error signal is further compared with a fixed frequency RAMP waveform derived from the internal oscillator to generate a pulse-width-modulated signal. This PWM signal drives the external N-Channel Power FETs via the TGDDQ and BGDDQ pins. External inductor L and capacitor COUT1 filter the output waveform. The VDDQ output voltage ramps up at a pre-defined soft-start rate when the IC enters state S0 from S5. When in normal mode, and regulation of VDDQ is detected, signal INREGDDQ will go HIGH to notify the control logic block. Input voltage feedforward is implemented to the RAMP signal generation to reject the effect of wide input voltage variation. With input voltage feedforward, the amplitude of the RAMP is proportional to the input voltage. For enhanced efficiency, an active synchronous switch is used to eliminate the conduction loss contributed by the forward voltage of a diode or Schottky diode rectifier. Adaptive non-overlap timing control of the complementary gate drive output signals is provided to reduce large shoot-through current that degrades efficiency.
Tolerance of VDDQ
The VDDQ regulator is a switching synchronous rectification buck controller directly driving two external N-Channel power FETs. An external resistor divider sets the nominal output voltage. The control architecture is voltage mode fixed frequency PWM with external compensation and with switching frequency fixed at 400 kHz " 15%. As can be observed from Figure 1, the
The tolerance of VFBDDQ and the ratio of external resistor divider R1/R2 both impact the precision of VDDQ. With the control loop in regulation, VDDQ = VFBDDQ x (1 + R1/R2). With a worst case (for all valid operating conditions) VFBDDQ tolerance of "1.5%, a worst case range of "2.5% for VDDQ = 1.8 V will be assured if the ratio R1/R2 is specified as 1.2500 "1%.
Table 1. State, Operation, Input and Output Condition Table
Input Conditions Mode S5 S5 S0 S3 VCCA Low X High High VOCDDQ X Low High High VDDQEN X X High High VTTEN X X High Low FPWM X X X High Operating Conditions VDDQ H-Z H-Z Normal Standby VTTREF H-Z H-Z Normal Normal VTT H-Z H-Z Normal H-Z Output Conditions TGDDQ Low Low Normal Standby (Power- saving) Normal Low BGDDQ Low Low Normal Standby (Power- saving) Normal Low PGOOD Low Low H-Z H-Z
S3 S5
High X
High X
High Low
Low X
Low X
Normal H-Z
Normal H-Z
H-Z H-Z
H-Z Low
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NCP5214
VDDQ Regulator in Standby Mode (S3)
During state S3, a power-saving mode is activated when the FPWM pin is pulled to VCCA. In power-saving mode, the switching frequency is reduced with the VDDQ output current and the low-side FET is turned off after the detection of negative inductor current, so as to enhance the efficiency of the VDDQ regulator at light loads. The switching frequency can be reduced smoothly until it reaches the minimum frequency at about 15 kHz. Therefore, perceptible audible noise can be avoided at light load condition. In power-saving mode, the low-side MOSFET is turned off after the detection of negative inductor current and the converter cannot sink current. The power-saving mode can be disabled by pulling the FPWM pin to ground. Then, the converter operates in forced-PWM mode with fixed switching frequency and ability to sink current.
Fault Protection of VDDQ Regulator
This regulator is stable with any value of output capacitor greater than 30 mF. The VTT regulator will have an internal soft-start when it is transited from disable to enable. During the VTT soft-start, a current limit is used as a current source to charge up the VTT output capacitor. The current limit is initially 1.0 A during VTT soft-start. It is then increased to 2.5 A after 1.0 ms or VTT output is in regulation, whichever is earlier.
VTT Active Terminator in Standby Mode (S3)
VTT output is high-impedance in S3 mode.
Fault Protection of VTT Active Terminator
To provide protection for the internal FETs, bidirectional current limit is implemented, preset at the minimum of 2.5 A magnitude.
Thermal Consideration of VTT Active Terminator
During state S0 and S3, external resistor (RL1) sets the current limit for the high-side switch. An internal 35 mA current sink (IOC) at OCDDQ pin establishes a voltage drop across this resistor. Besides, an offset voltage at the magnitude of RL1xIOC is also developed at the non-inverting input of the current limit comparator. The voltage at the non-inverting input is compared to the voltage at SWDDQ pin when the high-side gate drive is high after a fixed period of blanking time (150 ns) to avoid false current limit triggering. When the voltage at SWDDQ is lower than that at the non-inverting input for a consecutive 15 internal clock cycles, an overcurrent condition occurs, during which, all outputs will be latched off to protect against a short-to-ground condition on SWDDQ or VDDQ. The IC will be reset once VCCA or VDDQEN is cycled.
Feedback Compensation of VDDQ Regulator
The VTT terminator is designed to handle large transient output currents. If large currents are required for very long duration, then care should be taken to ensure the maximum junction temperature is not exceeded. The 5x6 DFN-22 has a thermal resistance of 35_C/W (dependent on air flow, grade of copper, and number of vias). In order to take full advantage from this thermal capability of this package, the thermal pad underneath must be soldered directly onto a PCB metal substrate to allow good thermal contact.
VTTREF Output
The compensation network is shown in Figure 2.
VTT Active Terminator in Normal Mode (S0)
The VTTREF output tracks VDDQREF/2 at "2% accuracy. It has source current capability of up to 15 mA. VTTREF should be bypassed to analog ground of the device by 1.0 mF ceramic capacitor for stable operation. The VTTREF is turned on as long as VDDQEN is pulled high. In S0 mode, VTTREF soft-starts with VDDQ and tracks VDDQREF/2. In S3 mode, VTTREF is kept on with VDDQ. VTTREF is turned off only in S4/S5 like VDDQ output.
Supply Voltage Undervoltage Monitor
The VTT active terminator is a two-quadrant linear regulator with two internal N-channel power FETs. It is capable of sinking and sourcing at least 1.5 A continuous current and up to 2.4 A transient peak current. It is activated in normal mode in state S0 when the VTTEN pin is HIGH and VDDQ is in regulation. Its input power path is from VDDQ with the internal FETs gate drive power derived from VCCA. The VTT internal reference voltage is derived from the DDQREF pin. The VTT output is set to VDDQ/2 when VTT output is connecting to the FBVTT pin directly.
The IC continuously monitors VCCA and VIN through VCCA pin and OCDDQ pin respectively. VCCAGD is set HIGH if VCCA is higher than its preset threshold (derived from VREF with hysteresis). The IC will enter S5 state if VCCA fails while in S0 and both VDDQEN and VTTEN remain HIGH.
Thermal Shutdown
When the chip junction temperature exceeds 150_C, the entire IC is shutdown. The IC resumes normal operation only after the junction temperature dropping below 125_C.
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NCP5214
APPLICATION INFORMATION
Overcurrent Protection
The OCP circuit is configured to set the current limit for the current flowing through the high-side FET and inductor during S0 and S3. The overcurrent tripping level is programmed by an external resistor RL1 connected between the OCDDQ pin and drain of the high-side FET. An internal 35 mA current sink (IOC) at pin OCDDQ establishes a voltage drop across the resistor RL1 at a magnitude of RL1xIOC. Besides, an additional offset voltage VOFFSET of 25 mV is developed at the non-inverting input of the current limit comparator. The voltage at the non-inverting input is then compared to the voltage at SWDDQ pin when the high-side gate drive is high after a fixed period of blanking time (150 ns) to avoid false current limit triggering. When the voltage at SWDDQ is lower than the voltage at the non-inverting input of the current limit comparator for a consecutive 15 internal clock cycles, an overcurrent condition occurs, during which, all outputs will be latched off to protect against a short-to-ground condition on SWDDQ or VDDQ. i.e., the voltage drop across the Rds(on) of high-side FET developed by the drain current is larger than the voltage drop across RL1 plus the additional offset voltage, the OCP is triggered and the device will be latched off. The overcurrent protection will trip when a peak inductor current hit the ILIMIT determined by the equation:
ILIMIT + RL1 IOC ) VOFFSET Rds(on)
To avoid false triggering the overcurrent protection in normal operating load range, calculate the RL1 value from the above equation with the following condition: 1. The minimum IOC value from the specification table, 2. The maximum Rds(on) of the MOSFET used at the highest junction temperature, 3. Determine ILIMIT for ILIMIT > IOUT(MAX) + DIL/2. Besides, a decoupling capacitor CDCPL should be added closed to the lead of the current limit setting resistor RL1 which connected to the drain of the high-side MOSFET.
Soft-Start
A VDDQ soft-start feature is incorporated in the device to prevent surge current from power supply and output voltage overshot during power up. When VDDQEN, VCCA, and VOCDDQ rise above their respective upper threshold voltages, the external soft-start capacitor Css will be charged up by a constant current source, Iss. When the soft-start voltage (Vcss) rises above the SS_EN voltage (X50 mV), the BGDDQ and TGDDQ will start switching and VDDQ output will ramp up. When the soft-start voltage reaches the SS_OK voltage (XVref + 50 mV), the soft- start of VDDQ is finished. The Css will continue to charge up until it reaches about 2.5 V to 3.0 V. The soft-start time tss can be programmed according to the following equation:
tss [ 0.8 Css Iss
Since the MOSFET Rds(on) varies with temperature as current flows through the MOSFET increases, the OCP trip point will also varies with the MOSFET Rds(on) temperature variation. The IOC temperature coefficient of 3200 ppm is used to compensate the Rds(on) temperature variation.
Ceramic capacitors with low tolerance and low temperature coefficient, such as B, X5R, X7R ceramic capacitors are recommended to be used as the Css. Ceramic capacitors with Y5V temperature characteristic are not recommended.
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NCP5214
VCCA VIN (VOCDDQ)
VDDQEN VTTEN is Don't Care in S5 10 ms VTT Soft-start X1.0 ms VTT in H-Z VTT Soft-start X1.0 ms
VTTEN VDDQ Soft-start
VDDQ
VTT
VTTREF PGOOD Operating Mode S5 thold X 200 ms
S0
S3
S0
S5
VCCA goes above 4.4 V to enable the IC. VDDQEN goes HIGH, VDDQ and VTTREF are enabled but not activated until VIN goes above threshold of 3.5 V. VTTEN goes HIGH, VTT is enabled but not activated until VDDQ is good.
PGOOD goes HIGH.
VTTEN goes LOW to activate S3 mode and to turn off VTT.
INREGDDQ goes HIGH, VTT goes into normal mode. VTTEN goes HIGH, VTT goes into normal mode.
Both VDDQEN and VTTEN go LOW to trigger S5 mode; VDDQ, VTT, VTTREF are disabled, then INREGDDQ and PGOOD goes LOW.
VIN goes above the threshold, the VDDQ and VTTREF go into normal mode.
Figure 3. Powerup and Powerdown Timing Diagram
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NCP5214
PACKAGE DIMENSIONS
DFN-22 MN SUFFIX CASE 506AF-01 ISSUE O
A B
NOTES: 1. DIMENSIONS AND TOLERANCING PER ASME Y14.5M, 1994. 2. DIMENSIONS IN MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINALS AND IS MEASURED BETWEEN 0.25 AND 0.30 MM FROM TERMINAL 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. MILLIMETERS MIN MAX 0.80 1.00 0.00 0.05 0.20 REF 0.18 0.30 6.00 BSC 3.98 4.28 5.00 BSC 2.98 3.28 0.50 BSC 0.20 --- 0.50 0.60
D
PIN 1 LOCATION
E 0.15 C 0.15 C 0.10 C A 0.08 C SIDE VIEW D2
22 X
TOP VIEW
A1 (A3)
C
SEATING PLANE
DIM A A1 A3 b D D2 E E2 e K L
L
1
e
11
22 X
K
22 22 X 12
E2
b 0.10 C A B 0.05 C NOTE 3
BOTTOM VIEW
SOLDERING FOOTPRINT
4.200 0.165 0.8050 0.0316
5.310 0.209 3.700 0.146
0.5000 0.0196
0.280 0.011
SCALE 8:1 mm inches
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13
NCP5214
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
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14
NCP5214/D

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